ISL12020MIRZ-T7A【PDF 20/34 页】IC RTC/CALENDAR TEMP SNSR 20DFN

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ISL12020M

FN6667.5

December 13, 2011

All I2C interface operations must begin with a START condition,

which is a HIGH to LOW transition of SDA while SCL is HIGH. The

ISL12020M continuously monitors the SDA and SCL lines for the

START condition and does not respond to any command until this

condition is met (see Figure 16). A START condition is ignored

during the power-up sequence.

All I2C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL is

HIGH (see Figure 16). A STOP condition at the end of a read

operation or at the end of a write operation to memory only

places the device in its standby mode.

An acknowledge (ACK) is a software convention used to indicate

a successful data transfer. The transmitting device, either master

or slave, releases the SDA bus after transmitting eight bits.

During the ninth clock cycle, the receiver pulls the SDA line LOW

to acknowledge the reception of the eight bits of data (see Figure

17).

The ISL12020M responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and once

again, after successful receipt of an Address Byte. The

ISL12020M also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an ACK

after receiving a Data Byte of a read operation.

Device Addressing

Following a start condition, the master must output a Slave Address

Byte. The 7 MSBs are the device identifiers. These bits are

“1101111” for the RTC registers and “1010111” for the User SRAM.

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W bit is a “1”, a read

operation is selected. A “0” selects a write operation (refer to

Figure 19).

After loading the entire Slave Address Byte from the SDA bus, the

ISL12020M compares the device identifier and device select bits

with “1101111” or “1010111”. Upon a correct compare, the device

outputs an acknowledge on the SDA line.

Following the Slave Byte is a one byte word address. The word

address is either supplied by the master device or obtained from an

internal counter. On power-up, the internal address counter is set to

address 00h, so a current address read starts at address 00h. When

required, as part of a random read, the master must supply the 1

Word Address Bytes, as shown in Figure 20.

In a random read operation, the slave byte in the “dummy write”

portion must match the slave byte in the “read” section. For a

random read of the Control/Status Registers, the slave byte must be

“1101111x” in both places.

Write Operation

A Write operation requires a START condition, followed by a valid

Identification Byte, a valid Address Byte, a Data Byte, and a STOP

condition. After each of the three bytes, the ISL12020M

responds with an ACK. At this time, the I2C interface enters a

standby state.

Read Operation

A Read operation consists of a three byte instruction, followed by

one or more Data Bytes (see Figure 20). The master initiates the

operation issuing the following sequence: a START, the

Identification byte with the R/W bit set to “0”, an Address Byte, a

second START, and a second Identification byte with the R/W bit

set to “1”. After each of the three bytes, the ISL12020M responds

with an ACK. Then the ISL12020M transmits Data Bytes as long as

the master responds with an ACK during the SCL cycle following

the eighth bit of each byte. The master terminates the read

operation (issuing a STOP condition) following the last bit of the

last Data Byte (see Figure 20).

The Data Bytes are from the memory location indicated by an

internal pointer. This pointer’s initial value is determined by the

Address Byte in the Read operation instruction, and increments

by one during transmission of each Data Byte. After reaching the

memory location 2Fh, the pointer “rolls over” to 00h, and the

device continues to output data for each ACK received.

FIGURE 18. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)

IDENTIFICATION

BYTE

DATA

BYTE

SIGNALS FROM

THE MASTER

SIGNALS FROM

THE ISL12020M

WRITE

SIGNAL AT SDA

00 00

11 1

ADDRESS

BYTE

FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES

SLAVE

ADDRESS BYTE

DATA BYTE

WORD

ADDRESS

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